Herbert Waggener : An Unknown Giant of Science

Poor mensch - not even a wikipedia page on him.. He has to tell his own story :

http://www.lulu.com/spotlight/hawaggener

I entered Missouri University in 1954 to major in Physics. When I entered, I was a little undereducated, and had to work my way through school, but by the second year, I had reached parity with my peers from St. Louis and other larger schools. I was awarded scholarships by the Physics Department in each of my next three years, and joined delta sigma phi fraternity in my junior year to provide some rounding out. In my senior year, I flamed out, and academically crashed and burned. My marriage in 1958 worked well, and I once more achieved excellence at San Diego State College. I joined the Navy Electronics Lab in 1959 and received a Masters in Physics in 1960. While in San Diego, we had three bright, healthy children, and in 1961 I accepted a job at AT&T Bell Labs, Murray Hill NJ to work in semiconductor technology. (The Education and Domestication of a Bulldog)

I joined Bell Labs in 1961, wanting to prove that I could compete and contribute to the progress of silicon semiconductor technology, in the midst of an amazing group of giants. After somemeandering about, I was successful in a small way. Among other things, I invented alcoholic alkaline anisotropic etches for forming isolation slots, electrochemically controlled thinning for forming very thin silicon structures, and applied them to making high speed bipolar integrated circuits. My group and I were drafted into a massive technology development program to help develop a very advanced double level tungsten gate MOS memory technology. My group and I made significant contributionsd to the project before I left to join the Teletype Corporation in Skokie Illinois. I left some small footprints on the sands of time while at Bell Labs, but wanted to find a new venue for my efforts. (On the Bell Lap, Walking Among Giants)

LTspice and XFAB - The Unbeatable Combination

A work of art - a 4 MHz switcher with SKIP mode implemented. Everything's macromodeled at this point except the switches and some of the logic cells.. Showing a sweep of the load with VIN 3.3V, Vo 5.625V (nom, this is the load-line architecture).

Now, time to try prototyping a hysteretic boost using what I just learned today..

Hier Findes Sie der Noise Potpourri aus Herr Doktor William Marshall Leach

www.pearl-hifi.com/06_Lit_Archive/07_Misc_Downloads/Noise_by_Marshall_Leach.pdf

With some Bunnie Huang style disclaimers about fair use.

Intuitively Please : R1C1 Into R2C2

Intuitively, say what the bode plot should be. That part's not hard - you can work from what you'll get at f=0 and f=0 (what do caps do at both extremes?)

But, can you intuitively say what the pole and zero are? The math is easy, you could do this in a minute.. but.. think..

You already have a Thevenin circuit - so, if you make a Norton equivalent, what current do you get? And into what load? Get it - the load is everything in parallel - so, since that load looks like a short at infinite freq, obviously you have a pole at W = 1/(R1||R2 (C1 + C2)) . Easy.

Zero? What current do you get in your Norton equivalent? You have a part through an R and a C - at high frequency, it goes up because of the cap - so, obviously a pole - and, the frequency has to be W = 1/ (R1 C1). Childishly simple..

Digital Is Hard

Thought occurred to me today that what stands between me and being a successful subsystem designer (understand tradeoffs between the various topologies and control-schemes for power delivery) is a weakness with rapid digital prototyping..

It's easy to think of if-thens in your head. But how do you translate them into digital gates?

We're talking asynchronous stuff here - and not something neatly wrapped up in a box like a state-machine. Even an asynchronous one would be easy..

Give Me a Fish, Or, Teach Me ... LTspice Behavioural OR Gate

How do you make the symbol the easy way :

Open the one they have in Digital. Save As a copy.
Open in text editor, change SymbolType CELL to BLOCK.
Remove the Prefix and SpiceModel lines.
Add the SYMATTR SpiceLine thing to provide default values for the params.

That's it - now you know how to make your own models super easy..

For instructions, see older post on the AND gate below.

---------------------- first file, save as mdl_or.asc (schematic)
Version 4
SHEET 1 1152 680
WIRE 48 80 16 80
WIRE 560 112 448 112
WIRE 64 144 16 144
WIRE 624 160 512 160
WIRE 512 176 512 160
WIRE 240 192 128 192
WIRE 384 192 320 192
WIRE 464 192 384 192
WIRE 128 256 128 192
WIRE 368 288 352 288
WIRE 384 288 384 256
WIRE 384 288 368 288
WIRE 464 288 464 240
WIRE 464 288 384 288
WIRE 512 288 512 256
WIRE 512 288 464 288
WIRE 752 384 624 384
WIRE 384 400 256 400
WIRE 496 400 464 400
WIRE 576 400 496 400
WIRE 624 400 624 384
WIRE 64 416 16 416
WIRE 576 416 576 400
WIRE 256 432 256 400
WIRE 496 480 496 464
WIRE 576 480 576 464
WIRE 576 480 496 480
WIRE 624 480 576 480
WIRE 480 496 464 496
WIRE 496 496 496 480
WIRE 496 496 480 496
WIRE 128 576 128 336
WIRE 128 576 16 576
WIRE 256 576 256 512
WIRE 256 576 128 576
FLAG 16 144 b
IOPIN 16 144 In
FLAG 16 80 a
IOPIN 16 80 In
FLAG 16 576 g
IOPIN 16 576 In
FLAG 560 112 y
IOPIN 560 112 Out
FLAG 16 416 c
IOPIN 16 416 In
FLAG 624 160 Q
IOPIN 624 160 Out
FLAG 752 384 Qb
IOPIN 752 384 Out
FLAG 368 288 g
FLAG 480 496 g
SYMBOL bv 128 240 R0
SYMATTR InstName B1
SYMATTR Value V=if( (V(a,g) > Vth) | (V(b,g) > Vth) | (V(c,g) > Vth) , Vhigh, Vlow )
SYMBOL bv 256 416 R0
SYMATTR InstName B2
SYMATTR Value V=if( !((V(a,g) > Vth) | (V(b,g) > Vth) | (V(c,g) > Vth)) , Vhigh, Vlow )
SYMBOL res 336 176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1000
SYMBOL res 480 384 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1000
SYMBOL cap 368 192 R0
SYMATTR InstName C1
SYMATTR Value 1p
SYMBOL cap 480 400 R0
SYMATTR InstName C2
SYMATTR Value 1p
SYMBOL e 624 384 R0
SYMATTR InstName E1
SYMATTR Value 1
SYMBOL e 512 160 R0
SYMATTR InstName E2
SYMATTR Value 1
TEXT 712 160 Left 2 ;params : \nVth : input transition threshold\nVhigh : output high level\nVlow : output low level

---------------------- end first file

Version 4
SymbolType BLOCK
LINE Normal -32 32 -28 32
LINE Normal -32 96 -28 96
LINE Normal 12 48 32 48
LINE Normal -32 80 -24 80
LINE Normal -32 64 -20 64
LINE Normal -32 48 -24 48
CIRCLE Normal 32 88 16 72
ARC Normal -132 8 -20 120 -32 96 -32 32
ARC Normal -80 -12 28 96 -28 96 24 64
ARC Normal -80 32 28 140 24 64 -28 32
WINDOW 0 -8 8 Left 2
WINDOW 3 -8 128 Left 2
SYMATTR Description Behavioral OR gate with complementary outputs
SYMATTR SpiceLine Vth=1.5 Vhigh=3.0 Vlow=0
PIN -32 48 NONE 0
PINATTR PinName a
PINATTR SpiceOrder 1
PIN -32 64 NONE 0
PINATTR PinName b
PINATTR SpiceOrder 2
PIN -32 80 NONE 0
PINATTR PinName c
PINATTR SpiceOrder 3
PIN 32 80 NONE 0
PINATTR PinName Qb
PINATTR SpiceOrder 4
PIN 32 48 NONE 0
PINATTR PinName Q
PINATTR SpiceOrder 5
PIN -16 96 NONE 0
PINATTR PinName g
PINATTR SpiceOrder 6

---------------------- end 2nd file (mdl_or.asy - symbol )

LTspice Behavioural AND Gate

For that day when you're finally fed up with the one they've provided that's causing you to pull your hair out..

How : save the first file as mdl_and.asc. Save the second as mdl_and.asy in your working directory - that is, wherever you have the testbench you're going to simulate - so you can use this..

NOTE - if you're familiar with LTspice files, you should know that stuff displayed below maybe wrapped - that is lines that should all be on one "line" are displayed using 2.. Generally, all lines begin with a directive that's ALL CAPs.

---------------------------------------- first file (don't copy this line)
Version 4
SHEET 1 1392 680
WIRE 864 0 752 0
WIRE 752 16 752 0
WIRE 480 32 368 32
WIRE 624 32 560 32
WIRE 704 32 624 32
WIRE 368 96 368 32
WIRE 608 128 592 128
WIRE 624 128 624 96
WIRE 624 128 608 128
WIRE 704 128 704 80
WIRE 704 128 624 128
WIRE 752 128 752 96
WIRE 752 128 704 128
WIRE 160 160 112 160
WIRE 160 224 112 224
WIRE 992 224 864 224
WIRE 624 240 496 240
WIRE 736 240 704 240
WIRE 816 240 736 240
WIRE 864 240 864 224
WIRE 816 256 816 240
WIRE 496 272 496 240
WIRE 160 288 112 288
WIRE 736 320 736 304
WIRE 816 320 816 304
WIRE 816 320 736 320
WIRE 864 320 816 320
WIRE 720 336 704 336
WIRE 736 336 736 320
WIRE 736 336 720 336
WIRE 368 416 368 176
WIRE 368 416 112 416
WIRE 496 416 496 352
WIRE 496 416 368 416
FLAG 112 160 a
IOPIN 112 160 In
FLAG 112 224 b
IOPIN 112 224 In
FLAG 112 288 c
IOPIN 112 288 In
FLAG 112 416 g
IOPIN 112 416 In
FLAG 864 0 Q
IOPIN 864 0 Out
FLAG 992 224 Qb
IOPIN 992 224 Out
FLAG 608 128 g
FLAG 720 336 g
SYMBOL bv 368 80 R0
SYMATTR InstName B1
SYMATTR Value V=if( (V(a,g) > Vth) & (V(b,g) > Vth) & (V(c,g) > Vth) , Vhigh, Vlow )
SYMBOL bv 496 256 R0
SYMATTR InstName B2
SYMATTR Value V=if( !((V(a,g) > Vth) & (V(b,g) > Vth) & (V(c,g) > Vth)) , Vhigh, Vlow )
SYMBOL res 576 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1000
SYMBOL res 720 224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1000
SYMBOL cap 608 32 R0
SYMATTR InstName C1
SYMATTR Value 1p
SYMBOL cap 720 240 R0
SYMATTR InstName C2
SYMATTR Value 1p
SYMBOL e 864 224 R0
SYMATTR InstName E1
SYMATTR Value 1
SYMBOL e 752 0 R0
SYMATTR InstName E2
SYMATTR Value 1
TEXT 952 0 Left 2 ;params : \nVth : input transition threshold\nVhigh : output high level\nVlow : output low level

---------------------------------------- end first file (don't copy this line)

Version 4
SymbolType BLOCK
LINE Normal -32 32 -12 32
LINE Normal -32 96 -12 96
LINE Normal -32 96 -32 32
LINE Normal 16 48 32 48
CIRCLE Normal 32 88 16 72
ARC Normal -44 96 20 32 -12 96 -12 32
WINDOW 0 16 24 Left 2
WINDOW 3 16 112 Left 2
SYMATTR Description Custom behavioural AND gate
SYMATTR SpiceLine Vth=1.5 Vhigh=3.0 Vlow=0
PIN -32 48 NONE 0
PINATTR PinName a
PINATTR SpiceOrder 1
PIN -32 64 NONE 0
PINATTR PinName b
PINATTR SpiceOrder 2
PIN -32 80 NONE 0
PINATTR PinName c
PINATTR SpiceOrder 3
PIN 32 80 NONE 0
PINATTR PinName Qb
PINATTR SpiceOrder 4
PIN 32 48 NONE 0
PINATTR PinName Q
PINATTR SpiceOrder 5
PIN -16 96 NONE 0
PINATTR PinName g
PINATTR SpiceOrder 6

---------------------------------------- end second file (don't copy this line)

Linux Catching Up to Windows in User Experience

By the look of things, enough people have clamoured about the lack of Autohotkey on Linux that Dekter has done something about it :

https://code.google.com/p/autokey/
https://www.youtube.com/watch?v=4KV_B6dBFHA
http://beginlinux.com/desktop_training/ubuntu/autokey-video-tutorial

LTspice : An NMOS Current-Sense Model for a Boost

Comes in handy when you're designing a peak-current-mode boost :

Basically use the bi component which lets you do some useful stuff (i.e., write code to do fancy models). In this case, it's a simple model. You only want to pass on the current when the FET is ON.

Put in a loop with the appropriate (not 100%) hooks to skip pulses at light load :

Learning from the Humble D Flip Flop

I was lamenting to a friend the other day how unproductive I am without the infrastructure of a big company. One thing an IC designer misses is the standard-cell libraries you get for free when you're with an established house. So, my current endeavours calling for a D-Flip-flop with asynchronous reset, I googles and gets this :

So, after reading this, I'd say : "Del Greco : More Harm Than Good". Why would you put something up like this in the age of LTspice, when you can get your TA or whoever to check it out? See how the thing simulates :

Crap! But, as George would read out, Prof. Del Greco is truly and utterly guilty of nothing more than trying to do his duty under difficult circumstances. Here's a class act :

http://www.ee.cuhk.edu.hk/~qzhao/ELE2120_files/ELE2120_tuto7.pdf

Popping Pills

Real time puzzle solving. Let's see if I'm right. I haven't felt too well lately, but managed some sleep yesterday during the day and felt refreshed. Didn't sleep too bad at night either.. Feel some good muscle tone. Despite not doing Lumosity for weeks, pulled off 210k+ on Penguin P. So..

RAY: You're on a medication regime in which you are to take daily one tablet of A and one of B. So, you have two little pill containers. One says "Pill A," and one says "Pill B." You must be careful. Taking two or more B's can have unpleasant side effects, or can even be fatal. In order for the B to be effective, it must be accompanied by the A pill.

TOM: So, you gotta take one A and one B. Got it.

RAY: Right. You open up the A bottle and one A pill kind of jumps out into your palm. You open the B bottle, and you accidentally get two Bs falling out of the bottle. But here's the problem: They look exactly the same. Both kinds of pills are blue, they're the same size, they're the same weight. And as soon as they fall in there, they get mixed up, so now you have three pills, but you can't tell what the heck you’ve got. The pills cost a hundred bucks apiece, and you can't throw them away.

How can you make sure that you get your daily dose of A and B without wasting any of the pills?

What would Jerome do?

Add one more pill A, put all 4 pills in a mortar, grind with a pestle and mix thoroughly. Then, take half of that mix today and the rest tomorrow.

If the pills are soluble in water, then you just add one more A pill, put all 4 in a class of water, dissolve, drink half today and the rest tomorrow?

How did I do? Sort of okay - they say cut each of the 4 pills in half and you're good - true.. Hmm..