Need to get this to the PDK master soon. A good example of the sort of stuff I do is on page 6 here, a good presentation anyways. One of the independent contractor guys says he uses Simucad and Tanner. We used Cadence at work and, while I miss it, I can think of a hundred ways it could be better. One of the heaviest and most inflexible tools you've ever seen. Not surprised they reported a 1.4b loss recently (q? yr?)
To do analog design:
1) Specifications - all values in the absolute maximum ratings (supply, temp) must be set in stone - they should not be TBD
2) Tool for schematic capture (meaning ability to generate a spice netlist)
3) spice - or, if working in RF, an equivalent of ADS or spectre
4) waveform viewer to view results.
5) spice models - this is the huge bottleneck - and depends heavily on a relationship with a vendor like MOSIS. But, there are other options like CMP and e-shuttle. Relationships are the key here - there are people who will let us put IP on their chips so we can test them
6) PDK - which really includes the spice models - we need to know what devices are available in the process, how to estimate die size, etc
7) corner spice models and mismatch models - design for manufacturing.
8) tool to use mismatch and statistical models to predict yield - this is important to productize a design. If you know that a parameter is guaranteed by design, then you don't need to test it - if you characterize it. But, if you know that you will have some yield loss which is acceptable, then you need to prescribe a test that can catch the bad chips
BTW, one name I've heard tossed about in the forums for cheaper analog design - compared to the Cadence suite is penzar : http://penzar.com/
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