That will be our LTspice project of the day : design an open-source version of the FAN4860 in LTspice using the NMOS and PMOS devices from the TSMC 0.35 um process. (Why? Because, though the 0.5 um process might suffice, those models aren't readily available).
What will you learn? You will learn pseudo-constant ON-time control. You might have heard of fixed-frequency voltage-mode and current-mode control - which ensure a well-defined switching frequency. By choosing this architecture, we avoid some issues inherent in the fixed-frequency approach like limited bandwidth and consequently diminished load-transient regulation performance. The chosen regulation scheme is not without drawbacks - mainly that the switching frequency is not well controlled - but it is good enough.
You will learn what is needed to provide true shutdown - ensure that there is no path from the input supply to the output when the converter is disabled. A poor way of providing this is to have an additional switch in series with the inductor - a scheme adopted by Texas Instruments on DSC PMICs.
You will learn what can be done to reduce the no load IQQ (quiescent current) from the existing 37 uA to less than 10 uA.
Points for extra effort from FCS : they state the soft-start peak input current is only guaranteed by design and not tested in production. Good to know - it's kind of understood if it's not a min/max..
Conveniently missing from the datasheet is any mention of the shutdown sequencing. When EN goes LO, do you immediately send the bulk of the PFET back to VIN thereby sending huge current through the diode? I doubt it.. What you could do is switch the PFET at a certain duty cycle (NMOS stays OFF all the time) till you have discharged Vout to close to VIN, or operate the PFET as a current source again - probably better - why have any noise if you can avoid it?
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